Optical spatial resolution, or the ability to clearly resolve closely placed structures, is important in many fields and of particular interest in the field of chip imaging equipment. Infrared optical techniques for silicon debug and fault isolation, such as emission microscopy (IREM), laser probing (LVP), time-resolved emission (TRE), and Laser Assisted Device Alteration (LADA), all rely on high-resolution microscope objective lenses which function in the near infrared (1.0-1.5 μm) portion of the electromagnetic spectrum.
With the advent of ultra-small features in silicon processes, the resolution of these microscopes, as denoted proportionately to the inverse of their numerical apertures (NA), have been improved to better resolve and collect data. For example, a modern 65 nm process technology features transistors whose gate length is just 35 nm; the gate essentially being the switch that turns a transistor on and off. By way of comparison, it has been said that approximately 100 of these gates could fit inside the diameter of a human red blood cell. To resolve images on microprocessors manufactured by this process, a 0.85 numerical aperture (NA) objective may be used with emission microscopy (IREM) and Laser Assisted Device Alteration (LADA) and a 1.4 NA oil immersion lens may be suitable with time resolved emission (TRE) and laser probing (LVP).
However, as features get smaller, a “solid immersion lens” (SIL) with numerical aperture of 2.45 may be needed for LVP and TRE. Eventually it is likely that a solid immersion lens (SIL) may be needed for all techniques, including LADA and IREM, due to the shrinking geometries of transistors and layout design rules.
A solid immersion objective comprises a final lens at the tip of the microscope objective that is generally hemispherical and has a flat side that is pressed into direct contact with the silicon. One major engineering challenge to be overcome in using such optical probe methods is that the integrated circuit (IC) under analysis must remain at a controlled temperature during the test, with chip cooling under realistic operating conditions as the main challenge.